The present invention relates to a device having a processor and a memory element positioned outside the processor and a device for linking the processor to the memory element, as well as a memory element.
Control units for controlling operating sequences, in particular in a motor vehicle, may exist. These may include, for example, control units for the motor controller, brake controllers, transmission controllers, etc. In addition to the processor and/or the computer, which contain internal memories, the digital parts contained in the control units may also include external memories, which are linked to the computer and/or the processor via a circuit board and/or circuit-board conductors. The external memories may be coupled to the processor via a circuit board and/or via circuit-board conductors. The link of this circuit board, however, may represent a limitation of the operating frequency of the coupling, since this link represents both a capacitive and an inductive load. The performance of this link, i.e., between computer and external memory, the transfer rate in particular, has a direct influence on the overall performance of the system in relation to the respective controller.
In order to achieve elevated performance, conventional link structures, such as SDRAM (synchronous dynamic random access memory), may allow the frequency to be increased, but with the limitation described above applying. A further problem for these links is that they were developed for relatively large distances between computer and memory and therefore may not achieve higher frequencies at certain limits.
Further increases in the clock frequency of the link between computer and external memory are promised by technologies such as DDRRAM (double data rate RAM), which is based on the SDRAM previously cited, as well as Rambus technologies such as RDRAM (Rambus DRAM) or DRDRAM (direct Rambus dynamic RAM).
A further problem arising in the event of increasing the link frequency is the emission and/or interference of electromagnetic signals and/or energy, due to which, for higher clock frequencies, more outlay may be required in the configuration for sufficient shielding to comply with the legal requirements and also to prevent undesired interference of signals, for example.
Therefore, a JEDEC standard (Joint Electronic Device Engineering Committee) was provided with the SSTL (stub series terminated logic) in order to increase the data transfer rate between a DRAM memory component and a CPU (central processing unit). In SSTL, the speed was increased through impedance adjustment of a transfer line, such as a bus, because reflecting waves, which were generated if a conventional low voltage method such as LVTTL (low voltage transistor transistor logic) was used, were reduced through the impedance adjustment. The SSTL interface thus offers a high data rate, but with higher EMC emission (electromagnetic compatibility) at the same time. Therefore, a non-differential bus interface was defined for DRAMs by the SSTL standard, which did implement a high data rate, but simultaneously implemented high EMC.
Thus, it has been shown that the related art may not provide optimal results in every regard.
In addition; in other technical fields, buses and/or bus systems, which are constructed in LVDS structure (low voltage differential signal), may exist as point-to-point links for coupling devices to a computer. This LVDS structure is standardized and known as a standard in accordance with ANSI/TIA/EIA-644. According to this standard, LVDS is used as a communication link between a computer and an associated monitor, for example.
Furthermore, the IEEE standard P1596.3-1995 defines the above-mentioned LVDS as a communication link between processors in multiprocessor systems, a point-to-point link also being constructed as bidirectional in half duplex operation in this case.
Therefore, an object of the present invention is to achieve a performance which is as high as possible, and to take the EMC problem, the emission in particular, into consideration, in order to avoid additional costs for reducing the emission and/or interference or the EMC problem in the device.
In the further description, LVDS and SSTL are cited as examples. This is not to be understood as restricting the object of the present invention. In general, any differential structure, LVDS in particular, and any structure having transistors which switch to voltage and ground, SSTL in particular, may be used according to the present invention. Therefore, the present invention is also illustrated for all differential and single-ended buses.
Therefore, according to the present invention, both interface functions may be implemented in one bus interface in a combined circuit logic and/or a combined structure. It may then be decided in the respective application whether the EMC rate in relation to emission and/or interference of electromagnetic signals (EMC problem) is acceptable, and accordingly SSTL function is to be used, or whether LVDS function is to be used due to the EMC problem, since a lesser EMC problem and/or EMC rate may also arise through the differential construction.
A memory element which is linkable to a processor via address and/or data lines may be provided, the memory element being positioned outside the processor, the address and/or data lines expediently each being implemented in a structure combining LVDS and SSTL, which has corresponding transmitters and receivers, the transmitter and receiver on the side of the memory element being integrated therein.
A device having a processor and a memory element positioned outside the processor, as well as a device for linking the processor to the memory element, may also be provided, the processor and the memory element being linked via address and/or data lines, the address and/or data lines each expediently being implemented in a structure combining LVDS and SSTL, which has corresponding transmitters and receivers.
In an example embodiment of the memory element and the devices, only the data lines are implemented in the structure combining LVDS and SSTL.
In a further example embodiment of the memory element and/or of the devices, an arbitrary number of the address and/or data lines are implemented as bit lines in a structure combining LVDS and SSTL.
In an example embodiment, the structure combining LVDS and SSTL is configured in such a manner that it is possible to switch between LVDS and SSTL functions of the structure by triggering at least one switching arrangement.
In this case, in an example embodiment, the at least one switching arrangement is implemented as a transistor, the transistor simultaneously being used as a supply voltage source Vcc for the SSTL function.
In a further example embodiment, at least two switching arrangements are triggered in order to switch between LVDS and SSTL functions, one of the at least two switching arrangement, the transistors in particular, being used as a power source for the LVDS function.
In a further example embodiment, the switching arrangement which is used to switch between LVDS and SSTL functions is implemented as a transistor having multiple control terminals, not all control terminals being activated for implementing the LVDS functionality.
Therefore, in the structure combining LVDS and SSTL, two address and/or data lines, which are usable in the switched-over state for the LVDS function, may be available as bit lines for an SSTL function.
Using this implementation, a high data rate and a low and/or favorable EMC may be implemented by one structure. Therefore, additional costs for reducing the EMC emission and/or interference may be largely avoided. According to the present invention, the object may therefore be achieved in a manner which takes both aspects cited, high data rate and EMC problem, into consideration in one application.